CPU: Main AIR

CPU: Main AIR#

The Main AIR (\(2^{22}\) rows) is the central instruction dispatch unit. It processes RISC-V instructions (main_planner), dispatches operations to coprocessors via the Operation Bus, and maintains the program counter and register state.

Constraints are evaluated via the ConstraintModule interface; Main uses the BytecodeConstraintModule backed by compiled expression bytecode from the proving key.

Instruction Execution#

Each row of the Main trace represents one clock cycle. The Main AIR decodes the current instruction and dispatches the operation to the appropriate coprocessor via the Operation Bus. It does not perform computation directly—all arithmetic, bitwise, and cryptographic operations are delegated.

Bus Interactions#

  • Operation Bus (5000), assumes. Dispatches operations with the tuple \((\mathrm{opcode},\; \mathrm{step},\; 0,\; \mathrm{addr},\; 0,\; \ldots)\). The coprocessor that handles this opcode proves the matching tuple.

  • ROM Bus (7890), assumes. Fetches instruction words from the Rom AIR. The tuple includes program counter, immediate values, and operand encodings.

  • Memory Bus (10), permutation. Issues memory loads and stores. The Mem AIR proves the corresponding memory operations.

  • Operation Bus (5000), direct update. Provides continuation anchoring: the initial state (boot address) and final state (end address) are published as direct global updates, checked by the global constraints.

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